A module is a unit of Verilog code that is used to describe a component. In Verilog-A, as in Verilog, a circuit is described with a hierarchical composition of modules. In addition, both Verilog and Verilog-A allow built-in simulator primitives to be used in the circuit description. In Verilog, those built-in primitives generally describe gates. In Verilog-A, the built-in primitives describe common circuit components, such as resistors, capacitors, inductors, and semiconductor devices. A module that simply refers to other modules is often referred to as a structural model, or a netlist.
Conversely, a module that uses equations to describe a component is referred to as a behavioral model. A module may contain both equations behavior and instantiations of other modules structure. It also may contain neither, in which case it is referred to as an empty module. In Verilog-A, components are constructed using nodes and branches.
A node is a point where the endpoints of branches may connect, and a branch is a single path between two nodes. The potential on a branch is equal to the difference of potentials of the nodes to which it is connected.
Signal flow, not electrical networks. Add to Watchlist Unwatch. Here again, that state machine may be more thoroughly verified using constrained random techniques than with analog signals. Appendix B: System Tasks and Functions. After the initial setup, AMSDMV allows the model validation simulations to be run with a set of regression scripts that can also be
You can describe any arbitrary component with a collection of nodes and branches. That description consists of two things: way that the nodes and branches connected their topology , and the way in which the potential and flow are related on each branch the branch relations. Thus, to describe a component in Verilog-A you must: define the nodes and branches, and then specify the behavior of each branch. To see how this is done, consider this simple example of a linear two-terminal resistor:. The first line defines the name of the component, in this case resistor , and the pins, which are nodes that the component shares with the rest of the circuit.
Pins are also referred to as ports or terminals. In this case the pins are t1 and t2. The second line declares the pins as being electrical, meaning that the potential of each pin is a voltage and the flow into the pin is a current. Verilog-A defines the flow on the pin to be positive if the motion is into the component.
The third line declares a parameter r for the component. Parameters are values that can be specified when you instantiate the resistor when you place a resistor into your circuit. The value or r given in the parameter declaration is the default value of the parameter, it is the value used if no value is given during instantiation. Parameters are treated as constants within the module, meaning that the value of r cannot be changed from within the module.
The fourth line declares a branch named res and indicates that it is connected between the t1 and t2 pins.
The branch voltage V res equals V t1 - V t2 , the difference in the voltages on the two terminals taken in the order given. Thus, the branch voltage is positive if the voltage on the first node listed in the declaration t1 is greater than the voltage on the second node listed. The current of the branch is accessed using I res. It is positive if the current flows from the first terminal specified when res was declared t1 to the second terminal specified t2.
At this point we have completed the topological portion of the description. The nodes and branches have been declared and arranged. We now know that there are two nodes, t1 and t2 , that are shared with the rest of the circuit, and that there is a single branch, res , that connects t1 and t2. The only thing left to do is to give the behavior of the branch, the branch relation.
The branch has been connected to electrical nodes, so the branch itself must be electrical. Thus, a relationship between voltage and current is required. In Verilog-A all behavior is given in an analog process , which is denoted with the analog keyword.
In this case, we only need one statement to define the behavior of the resistor, so it is sufficient to just give the analog keyword. If multiple statements are needed, then you would need to surround them with the begin and end keywords, as will be demonstrated shortly. The behavior of a branch is given using a contribution statement :. It specifies an equation that must be satisfied by the simulator.
Using contribution statement is the only way to affect the value of a branch potential or flow and indirectly the behavior of the greater circuit , and only branch potentials and flows may be the target of a contribution operator. Having said that, it is not always necessary to explicitly declare your branches. This resistor model could also have been given as:.
Analog Behavioral Modeling With The Verilog-A Language provides the IC designer with an introduction to the methodologies and uses of analog behavioral. Introduction. Behavioral Descriptions. Analog Model Properties. Statements for Behavioral Descriptions. Analog Statement.
In this case the resistor branch is created implicitly by combining t1 and t2 in the same access function. The voltage on t1 is greater than t2 if a positive value is contributed to the branch. The current on the branch is positive if it flows from t1 to t2.
The only way to affect the larger circuit is through branches. The functional model is too slow to simulate the time scales of interest but unlike its performance counterpart, the functional model makes sure the amplifier is connected properly. Bottom up verification: Suppose you have a device level model of a function block and you want to see how it performs in the larger system but the larger system is to complex to simulate at the same level of detail. You can model the testbench behaviorally with VerilogA while leaving the device of interest at the device level and save in simulation time.
Golden models: This is perhaps one of my more frequent applications. I need to write a model in MatLab or C.
I usually start from my library of VerilogA models because I can check VerilogA models in circuit level test benches. I generate test vectors to help debug the translation into MatLab or C. In this mode, the VerilogA model is a golden model that brigdes the gap between the higher level model and the circuit model. Diagnostics: I can't tell you how many times someone has come to me with an set of annoying symptoms observed in the lab and a long list of hypothesized root causes.
The proper course of action of course depends on a correct diagnosis of the symptoms. The real issue is that the system is either a chip with no test points, or a sealed box with months of successful testing under its belt that no one wants to void by breaking the seal. The only way to test the various hypotheses is through modeling and simulation. Behavioral modeling can help focus your efforts by simplifying circuitry that is not under suspicion and by importing lab measurements directly into the simulation.
For example, you can fit a curve to I-V measured data to model a device more accurately than any simulator primitive model. I suppose this is a kind of bottom-up verification. However, I differentiate it from what the CAE vendors call bottom-up verification because it rarely feels like the scheduled task the CAE sales people describe. This task is never scheduled. This task is usually done with an acute sense of urgency imposed upon you by your entire management chain. Test Definitions: You are in the early stages of a design; you are specifying something that does not yet exist.
Sometimes, the parameters you specify can not be directly measured. In this case, you can use behavioral modeling to translate your theoretical parameters into easily measured parameters by simulating a test. Customer support: I only come across this one once or twice. You have a potential customer who wants to simulate your product in his system before he buys; he wants a test drive.
You do not want to give him your detailed model because you then expose your intellectual property. Instead, you provide a behavioral VerilogA model that simulates the specifications, and perhaps then some, but does not expose the details of how you achieve those cool specifications. Re: [need help] veilogA design flow Reply 12 - Mar 10 th , , pm. Question 2: Spectre simulation is carve up to direct simulation spectre and socket simulation spectreS ,why?
Re: [need help] veilogA design flow Reply 13 - Mar 11 th , , pm. I really appreciate your help! Eugene, it's a full-scale description! Andrew, I agree with you. All Rights Reserved.
All rights reserved. Send comments or questions to editor designers-guide. Consider submitting a paper or model. It can be run from within the analog design environment easily enough, and I guess you could write an OCEAN script to do it from the command line, but if you're unfamiliar with the tool, start off with doing it interactively. The reasons for this is that this is a two simulator approach.
The ADE environment will partition the design into two netlists based on which parts need to be in which domains , and so any change of the partitioning requires a whole new netlist. You need to start off by using the hierarchy editor to create a "config" view, which tells the netlisters which views are to be used for which blocks - and then you simulate using the config view in ADE. I can't really go through the whole flow here - it's in the documentation I'm sure - but once you've got it all set up, then you could write out your session as an OCEAN script, and then it could be run in batch mode.
Alternatively you might want to consider using AMS Designer I pointed at a tutorial for that in an earlier post as this is a single simulator approach, and in my opinion considerably easier to use, especially if you're going to want to be able to use it standalone. Quote: Question 2: Spectre simulation is carve up to direct simulation spectre and socket simulation spectreS ,why? There are two interfaces to spectre in the Analog Design Environment.
The reason that this was done was that many simulators did not have a rich language which supported parameterisation, at least not in a consistent way. So, what happened was that with spectreS, netlists were created using cdsSpice's language and then cdsSpice would handle all the parameter evaluation, and would spit out a "final" netlist with all parameters expanded for spectre to simulate. Now, as you can imagine, having a second tool in the way was hardly optimal - every time you changed a parameter it had to completely recreate the netlist for spectre.
Also, it tended to make each simulator look like a basic spice simulator, and it was hard to access the full capabilities of the simulator. So, back in IC, a new "spectre" direct interface was added.