Enhancing electronic circuits with ad hoc testing circuitry—so-called Design for Test DFT —is a technique that enables one to thoroughly test circuits after production.
But this insertion of new elements itself may sometimes be a challenge, for bad choices could lead to unacceptable degradations of features of the circuit, while good choices may help reduce testing costs and circuit production costs. This chapter demonstrates how methods from Operations Research—a scientific discipline rooted in both mathematics and computer science, leaning strongly on the formal modeling of optimization issues—help us adress such challenges and build efficient solutions leading to real-world solutions that may be integrated into electronic design software tools.
Two power-reduction techniques are exploited to design a low leakage power NoC switch. First, the adaptive virtual channel AVC technique is presented as an efficient way to reduce the active area using a hierarchical multiplexing tree of VC groups. Second, power gating reduces the average leakage power consumption of the switch by controlling the supply power of the VC groups. The traffic-based virtual channel activation TVA algorithm is presented to determine traffic load status at the NoC switch ports. The TVA algorithm optimally utilizes virtual channels by deactivating idle VC groups to guarantee high leakage power saving without affecting the NoC throughput.
In this chapter, the problem of decoupling network optimization is discussed in detail. Swarm intelligence is used for maintaining power integrity in high-speed systems.
The optimum number of capacitors and their values are selected to meet the target impedance of the system. As CMOS technology scales to nanometer dimensions, its performance and behavior become less predictable. In conventional circuits, the impact of the inputs on reliability can be observed by the deterministic input patterns. However, in nanoscale circuits, the inputs behave probabilistically. The Bayesian networks technique is used to compute the reliability of a circuit in conjunction with the Monte Carlo simulations approach which is applied to model the probabilistic inputs and ultimately to determine sensitive inputs and worst-case input combinations.
Electrowetting-on-dielectric chips are gaining momentum as efficient alternatives to conventional biochemical laboratories due to their flexibility and low power consumption. In this chapter, we present a novel two-stage metaheuristic algorithm to optimize electrode interconnect routing for pin-constrained chips. The first stage models channel routing as a traveling salesman problem and solves it using the ant colony optimization algorithm.
The second stage provides detailed wire routes over a grid model. The algorithm is benchmarked over a set of real-life chip specifications. The quantum dot cellular automata QCA is a promising paradigm to overcome the ever-growing needs in size, power and speed. In this chapter we explore charge-confined low-power optimum logic circuit design to enhance the computing performance of a novel nanotechnology architecture, the quantum dot cellular automata.
We investigate robust and reliable diverse logic circuit design, such as hybrid adders and other binary adder schemes, among them bi-quinary and Johnson—Mobius, in QCA.
We also examine zero-garbage lossless online-testable adder design in QCA. Multivalued logic circuit design, with potential advantages such as greater data storage, fast arithmetic operation, and the ability to solve nonbinary problems, will be important in multivalued computing, especially in the ternary computing paradigm.
Wireless capsule endoscopy WCE enables screening of the gastrointestinal tract by a swallowable imaging system. However, contemporary WCE systems have several limitations—battery, low processing capabilities, among others—which often result in low diagnostic yield. In this chapter, after a technical presentation of the components of a standard WCE, the authors discuss the related limitations and introduce a new concept of smart capsule with embedded image processing capabilities based on a boosting approach using textural features.
We discuss the feasibility of the hardware integration of the detection—recognition method, also with respect to the most recent FPGA technologies. Programme Structure This programme comprises 8 courses distributed evenly between the first two semesters, followed by a MSc diploma thesis reporting on the outcome of a substantial research project completed during the third semester.
Courses may be taught in English. The programme has been offered for 13 years and is reinstated anew according to the Greek law.
It will prepare you for a diverse range of exciting careers — not only in the digital media and computational intelligence field, but also in areas such as medical informatics, finance, innovation, consultancy, project management, and government agencies. Entry requirements A degree or an international equivalent is required in computer science or electrical and computer engineering or a numerate physical science discipline. The list of qualifications, the application procedure, and the governing policies will be published at the website upon programme approval by the Ministry of Education, Research, and Religious Affairs.
Autumn Semester 4 elective courses. Spring Semester 4 elective courses. Biosignal Analysis — Neuroinformatics. Computational Intelligence — Statistical Learning.
Materials Chemistry. This second of two related volumes addresses digital and network designs and applications, with 12 chapters grouped into parts on digital circuit design, network optimization, and applications. Methods in Ecology and Evolution. This image understanding can be seen as the disentangling of symbolic information from image data using models constructed with the aid of geometry, physics, statistics, and learning theory. The brief can include data describing restrictions and various parameters such as material types, available production methods, budget limitations and time constraints.