Integrated circuit technologies for wireless communications

Integrated circuits for wireless communications
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OSA Privacy Policy. Need help? As a Doctoral Student you will carry out research work within a research team, publish research results in the most esteemed international fora, attend doctoral courses and complete your doctoral thesis within four years. Our Doctoral Students will enjoy a competitive salary, fully paid free time equivalent of holiday and benefits such as occupational healthcare.

The starting salary for a doctoral student is approx. The position will be for four years in which time the candidate is expected to finish his doctoral degree. Potential candidates will be interviewed for open positions in August The expected starting time for the research work is in the third quarter of This will cause a non-zero voltage drop and thus so-called conduction loss, resulting in reduced efficiency. Secondly, the transistor will have non-zero rise- and fall times, potentially causing the current and voltage to be non-zero simultaneously.

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Skip to main content. JPA en. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2 , a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1. The study module provides also sufficient and good background for doctoral studies in the wireless communications and RF systems field. The transmitter section converts the outbound symbol stream into an outbound RF signal that has a carrier frequency within a given frequency band e.

Also CMOS subthreshold current will contribute to this. Thirdly, dynamic losses due to charging and discharging of parasitic capacitors must be taken into account — the switching losses. These are proportional to the switching frequency f , and will likely dominate for RF applications.

External elements such as output networks may cause losses as well, for example a tuning or impedance transformation network consisting of on-chip or discrete passive elements. These inductors and capacitors will include parasitics such as capacitances or series resistances. These may cause power dissipation and thus reduce the amplifier efficiency. The on resistance of the device is then given by. Having a low resistance decreases the conduction losses caused by the switch. Other considerations of interest for PA design are the current density capacity and parasitic capacitances.

The former is important if high output power is desired and the supply voltage is low. A larger width increases the current capacity. The parasitic capacitance may, however, cause increased dynamic losses, thus potentially decreasing the efficiency especially at high frequencies. Now that general technology issues have been discussed, SM amplifiers for radio frequencies will be addressed in this section, and an overview will be given of specific CMOS implementations. In amplifier theory, several different switched-mode types are established: the classes D, E and F Cripps, , Raab, They will briefly be addressed below, before looking into CMOS implementations in the next section.

Class-D amplifiers use a double-switch structure, with a series resonance circuit see Figure 2. The output current is alternatingly supplied by each switch, similar to a push-pull configuration. The simplest implementation for the two switches is an inverter. In that case the voltage contains only odd harmonics, and the current even harmonics. Simplified schematic of a class-D amplifier, a. A voltage-mode amplifier, b. A current-mode amplifier.

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This amplifier may also be implemented as current-mode see Fig. Instead of having a series resonance circuit in series with the load, a parallel resonance circuit is then used at the output of the amplifier. In that case the current approximates a square-wave, containing odd harmonics, while the drain voltage for each device approximates a half-wave rectified sine wave. It has been shown that a high efficiency can be achieved, assuming the amplifier can be designed for Zero Voltage Switching Long et al. A class-E amplifier consists of a single switching device with a carefully tuned output network.

The voltage derivative, close to the timing point when the device is switched off, is designed to be very small so-called Zero Voltage Switching, ZVS so that potential static losses are kept very low. One of the characteristics of class-E is that large voltage peaks occur; thus, care must be taken to avoid high voltages across the CMOS device, as the breakdown voltage of CMOS devices is relatively low. A class-F amplifier is basically an amplifier with a current that approaches a half-wave rectified sine wave, and a voltage that approaches a maximally flat shape.

Tuning a limited number of odd-order harmonics of the fundamental signal is used to achieve this. Two different structures are in use for class-F design, depending on which harmonics are seen at the drain: Regular class-F for odd-order harmonics, that is, the voltage is approximately maximally flat, and inverse class-F for even harmonics, i. It must be noted that the inherent pulse shaping makes this amplifier less suitable for e. All three amplifier classes depend to some extent on a frequency-selective output network.

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Thus, their operation cannot be considered broadband. Research is progressing into variable output networks, where digital control signals are used to e. In such digitally assisted systems the use of CMOS technology, also for the PA, may lead to a higher level of integration. This will be addressed more extensively in the section on transmitter architectures.

These works initially focused on more or less linear amplifier structures such as class A, AB, B or C, but research has since then focused more on the switched-mode class-D, E and F, as higher clocking or switching speeds became available with improvements in CMOS technology. Su and McFarland presented a 0. Yoo and Huang presented a 0. These strategies allow for a higher supply voltage to be used, thus reducing the necessity for a low load impedance. Reynaert and Steyaert have presented a fully integrated 0.

As limited supply voltage is one of the major challenges in CMOS PA design, other strategies have been used to effectively add the output voltages, such as using a transformer to combine output power Aoki et al. However, generally this slightly impairs the efficiency, counteracting the intended advantage of a higher supply voltage. Apart from voltage stacking, current combining has been implemented Kavousian et al.

The latter two will be covered more in the section on transmitter architectures. As we have seen before, one of the basic requirements for power amplifiers in modern wireless communication systems is to accommodate envelope variations and to provide variable output power. Wireless communication standards have moved from constant-envelope, low- channel bandwidth to more complex signal shapes in order to increase data rates in limited bandwidth, resulting in variable envelope RF signals and larger channel bandwidths in the range of tens of MHz.

In SM amplifiers output power variation can be achieved by varying the supply voltage, by varying the duty cycle of the signal, by varying the load, or by a combination of these. In this section some transmitter architectures will be discussed that adopt such strategies; only the strategy of varying the load impedance will not be addressed here. On the transmitter architecture level, one of the classical methods of varying the output power is based on polar modulation, where a baseband Cartesian signal vRF t is first converted into its polar form, separating envelope amplitude and phase information, which are then processed separately and combined before being transferred to the antenna:.

Polar modulation is recently gaining more and more interest due to its potential to maintain linearity while having a relatively high efficiency even for lower output power, thus improving the average efficiency over a wide output power range. The envelope is used to control the PA supply level, while the phase signal is upconverted to RF and transformed to a constant envelope signal, driving the PA input. Thus, a non-linear PA can be used. Su and McFarland have demonstrated a CMOS implementation of an EER system, including a delta-modulated supply, a limiter, and envelope detectors, driving a switched-mode PA, resulting in significant linearity and efficiency improvements.

Envelope tracking ET describes a transmitter architecture where the Cartesian RF signal is amplified by means of a linear amplifier, with its supply controlled by the envelope of the signal Hanington et al. One of the main advantages is that the bandwidth of the PA input signal is not expanded, but a linear amplifier generally has a lower efficiency than a SM amplifier. However, requirements on the envelope signal and timing are less stringent Wang et al.

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Both the EER, ET and hybrid EER depend on utilizing an efficient power supply modulator, that must be able to handle the bandwidth of the envelope signal. Generally, independent of supply modulator type, a bulky low-pass filter must be used to filter out undesired signals such as noise or harmonics. If the duty cycle D of a square-wave signal is changed, the output power at the fundamental frequency will be changed according to.

Implementations exist with discrete steps as well as continuous change Yang et al. A major advantage of these strategies is that no DC-DC converter is necessary; A disadvantage is that linearity may be worse compared to an amplifier where the supply voltage is changed, possibly resulting in tougher requirements for digital predistortion.

Moreover, the efficiency drops rapidly at small duty cycles Cijvat et al. Smely et al. Yang et al. Variable gate bias was used Cijvat et al. The proposed architecture uses the envelope signal to control the gate bias, and the RF signal is assumed to be sinusoidal, containing only the phase information. For this amplifier structure, loss mechanisms as discussed in section 2 cause a drop in drain efficiency for lower output powers.

It is likely that switching and harmonic losses are significant; the amplifier switches as often as for full output power, thus having roughly the same switching loss, and the harmonic content of a PWM signal increases for duty cycles other than 0.

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As can be seen in Figure 4. This is applied to the aforementioned nm CMOS class-D inverters, and simulation results are presented in Figure 5. Moreover, combining the two strategies will lead to greater transmitter complexity; the additional power that is required is not taken into account in the simulations.